When you want to do some computation on an FPGA, it is traditional to enter your design in a language like Verilog, and then to use automatic synthesis tools to turn your Verilog design into a “configuration bitstream” that can be fed to your FPGA to make it perform the computation you want. These synthesis […]Fuzzing FPGA synthesis tools — John’s Blog
A fuzzer is a program that generates random input for another piece of software. The random inputs produce bugs in the target software, oftentimes a crash, but sometimes a security flaw. They’re useful for analyzing the robustness and correctness of a computer program’s capability to handle arbitrary user input.
John Wickerson & his students wrote a fuzzer for FPGA (Field Programmable Gate Array) boards, churning out random Verilog programs for input into the IDE’s logic synthesizer. The logic synthesizer’s job is to turn high-level Verilog code into low-level logic , flipping the FPGA gates into proper configuration, i.e. a hardware implementation of the code. The study determines how often the synthesizer fails to turn Verilog code into the proper gate arrangement on the board. They also find different classes of bugs produced by the fuzzed synthesizer.
It’s a very interesting article. If you are not familiar with FPGA development, take a look at this link from Xilinx.